Job Details:
Job Description:
Own FPGA post-silicon validation for assigned domains/products: lead design bring-up, plan and execute PVT and non-PVT testing including regression, build scalable design/test automation, and drive debug to closure. High individual ownership with strong cross-team collaboration (DV, IPSS, Customer Support).
Key responsibilities
Lead design bring-up on FPGA/silicon:
Own validation covering PVT (corners, voltage/temp sweeps, fmax/margin, stress) and non-PVT (functional, feature, system)
Define, maintain, and scale regression suites (content, automation, overnight runs, fail triage, exit criteria)
Architect and deliver design/test automation in Python, Tcl, and C
Use RTL and on-chip debug to root-cause failures across HW, timing, firmware, and board
Set test plans, coverage expectations, and validation exit criteria for assigned work
Defines and delivers continuous improvement of silicon validation environment and methodologies
Debugs and resolves silicon bring up issues, documents the solutions, troubleshoots, and debugs silicon from prototype to production.
Partner with DV, IPSS, and Customer Support on correlation, integration, and customer/field issues
Mentor junior engineers; review bring-up quality, regression health, and documentation
Represent validation in milestone reviews and technical escalations
Preferred
Depth in one or more of: Ethernet, ANLT, PTP, D-PHY, CPRI, JESD, SerialLite, DP, HDMI, SATA, SAS
Thermal chamber / shmoo / margin characterization
Board/schematic literacy; basic SI/PI for high-speed links
Mentored juniors or led a validation workstream
Emulation or pre-si to post-si correlation experience
Soft skills
Self-motivated technical owner for domain/product validation outcomes
Strong individual contributor who delivers with limited oversight
Effective team collaborator across DV, IPSS, Customer Support, and design
Qualifications:
B.E. / B.Tech / M.S. in ECE, EE, Computer Engineering, or related
5–8 years experience in post-silicon / FPGA / HW validation or protocol bring-up, aligned to Grade 6 / 7
Proven ownership of design bring-up and HW validation through production-quality outcomes
Hands-on PVT and regression planning, execution, and fail analysis
Strong HW knowledge plus automation in Python, Tcl, and C
Solid RTL debug ability (Verilog/SystemVerilog or VHDL)
FPGA tool and lab proficiency (JTAG/debug, scopes/analyzers, protocol tools as applicable)
Demonstrated collaboration with DV, IP/integration (IPSS or equivalent), and customer-facing teams
Clear technical writing for plans, bugs, and status
Job Type:
Regular
Shift:
Shift 1 (India)
Primary Location:
Bengaluru, Karnataka, India
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.