Job Details:
Job Description:
About the Role
Altera is seeking a Senior Lead Engineer - Design Verification to provide hands-on technical leadership for the verification of next-generation FPGA, programmable SoC, and platform solutions. This senior individual-contributor role will shape verification architecture, methodology, and execution for complex digital subsystems and full-chip integrations.
In this role, you will define scalable verification strategies, develop reusable verification environments, and drive coverage-driven closure from early architecture through silicon and product readiness. The successful candidate combines deep SystemVerilog/UVM expertise with strong technical judgment, a high bar for verification quality, and the ability to influence engineering execution across global, cross-functional teams.
Responsibilities
Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems, including block, subsystem, and full-chip verification.
Define comprehensive verification plans that translate architectural intent and product requirements into measurable functional, performance, resilience, and coverage objectives.
Architect and develop scalable, reusable SystemVerilog/UVM verification environments, verification IP, scoreboards, reference models, constrained-random stimulus, checkers, and coverage models.
Establish and advance verification methodology, coding standards, testbench guidelines, regression practices, and automation that improve consistency, quality, reuse, debug efficiency, and predictability across programs.
Drive verification closure using functional, code, assertion, and cross coverage; identify coverage gaps, evaluate risk, and ensure readiness against defined exit criteria.
Partner closely with architecture and RTL design teams to clarify specifications, identify verification risks early, review microarchitecture, and resolve complex functional or performance issues.
Lead debug of difficult simulation, integration, and system-level failures; apply rigorous root-cause analysis and drive timely resolution across design, verification, firmware, and validation teams.
Develop and maintain scalable simulation, regression, build, and reporting infrastructure to support efficient development and release quality.
Collaborate with emulation, FPGA prototyping, physical design, CAD, firmware, software, board, and post-silicon teams to ensure verification intent is carried through implementation, bring-up, and product delivery.
Provide technical mentorship and verification leadership through methodology reviews, test-plan reviews, code reviews, and hands-on guidance to engineers across the organization.
What You Will Bring
You are a hands-on verification leader who combines deep technical expertise with a practical, systems-level perspective. You bring disciplined engineering judgment, a collaborative leadership style, and a passion for building the verification foundations that enable Altera to deliver differentiated, high-quality programmable solutions.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$231,500 - $330,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
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Qualifications:
Minimum Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, with 15+ years of relevant experience in design verification for FPGA, ASIC, SoC, or semiconductor products; advanced degree preferred.
Demonstrated technical leadership delivering verification for complex digital subsystems or products from…