NOC Senior Design Engineer
Location: On Site Job Type: Full Time : Malaysians only and/or have permit to work in Malaysia Industry: Semiconductor, Network-on-Chip (NoC), Chip Design
Role Overview
We are seeking a Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involved architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs.
Key Responsibilities
• NoC Architecture & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors, components, ensuring performance, area, and power efficiency.
• Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency.
• Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues.
• Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams.
• Integration & Customization: Work on custom NoC configurations, integrating third- party IPs, and tailoring interconnect solutions for specific applications.
• Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools.
• Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.
Requirements • Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or related field. • Have experience in NOC RTL Design or experience in RTL Design, bonus if has interconnect architectures • Strong expertise in Verilog/SystemVerilog RTL design and synthesis-friendly coding. • Hands-on experience with NoC topologies (mesh, ring, torus, crossbar, etc.) and flow control
techniques. • Proficiency in performance modeling, simulation, and debugging. • Experience with industry-standard EDA tools for synthesis, static timing analysis (STA), and power analysis. • Strong understanding of on-chip communication protocols (AXI, CHI, PCIe, CXL, etc.). • Excellent problem-solving skills and ability to work in a fast-paced, collaborative environment. Preferred: • Experience with NoC-specific tools (Arteris, NetSpeed, OpenSoC, etc.). • Familiarity with cache coherence protocols (MESI/MOESI, CCIX, etc.). • Knowledge of hardware security, fault tolerance, and reliability in NoC design. • Scripting skills (Python, Perl, Tcl) for automation and debugging. • Experience with chiplet interconnects and heterogeneous computing architectures.