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The Lead Analog Layout Engineer shapes the high-speed silicon behind Ciena's WaveLogic coherent optical communications products by owning critical analog and mixed-signal layouts from feasibility through tapeout. This hands-on individual-contributor technical leadership role sets layout direction, coordinates delivery with circuit designers and layout contributors, and advances implementation in advanced CMOS technologies. The role builds on more than 30 years of team innovation in high-speed ADC and DAC macros for coherent optical transmission while extending capabilities into high-speed SerDes.
How you will make an impact:
Own assigned layout projects from feasibility and floorplanning through implementation, physical verification, integration, and tapeout readiness.
Define project scope, implementation plans, effort estimates, milestones, and review checkpoints with circuit designers and engineering leads; coordinate contributors, track dependencies, and resolve implementation bottlenecks.
Lead layout reviews and quality checks with the layout team and circuit designers.
Partner with circuit designers to establish implementation constraints and evaluate performance, area, device matching, parasitics, isolation, and reliability tradeoffs.
Develop layout strategies for performance-critical circuits and high-speed signal paths; review extracted parasitics and implement targeted improvements.
Drive physical-verification and reliability closure, including DRC, LVS, ERC, antenna, BUMP, EM/IR, and PERC checks.
Mentor junior engineers through hands-on problem-solving and design feedback; partner with CAD and AI/ML engineers on environment setup, tool evaluation, automation, reusable layout structures, RFIC and analog layout generation, PCell development, and design space exploration; communicate progress, risks, and corrective actions against milestones.
The must haves:
Education: Bachelor's degree or higher in Electrical Engineering, or a related field.
Experience: 5+ years of custom analog or mixed-signal IC layout experience, including ownership of complex layouts through successful tapeouts, independent technical decision-making, project delivery, guidance of layout contributors, and hands-on implementation.
Application of layout expertise in one or more circuit families, such as ADCs, DACs, SerDes, PLLs, high-speed amplifiers, or precision analog circuits.
Utilization of Cadence Virtuoso and Siemens Calibre, or comparable custom-layout and physical-verification tools.
Application of device matching, parasitic resistance and capacitance, coupling, high-frequency routing, shielding, ESD-aware layout, electromigration, and IR drop.
Application of deep-submicron CMOS processes, foundry design rules, device isolation, and layout-dependent effects to performance and reliability challenges.
Collaboration with circuit designers, analytical problem-solving, attention to layout quality, and communication of technical tradeoffs.
Nice to haves:
Practical experience with FinFET layout and advanced-node implementation.
Experience in high-speed SerDes or data converters.
Ansys Totem or comparable EM/IR tools and PERC-based ESD and reliability debugging.
Deep knowledge of noise isolation and shielding.
PCell development and layout automation skills.
Experience using AI-assisted coding tools to develop and validate layout-flow scripts, automation, and engineering utilities.
Pay Range:
The annual pay range for this position in Canada is C$141,700 - C$226,000.
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Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market…