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Applications accepted until further notice.
Meet the Team
The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact
As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips. You will:
Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
Implement and manage timing ECO strategies using tools like Tweaker/ PrimeTime .
Analyze quality and efficiency gaps, recommend tool , flow, and methodology improvements.
Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.
Evaluate and implement new timing methodologies; provide creative debugging solutions.
Contribute to best practices and drive methodology alignment across projects.
Minimum Qualifications
Meet one of the following (completed within the past 3 years or expected to be completed within the next 12 months):
-A Master's degree with 0 years of work experience; or
-A Bachelor's degree with 2 years of work experience.
Qualifying education and work experience should be in ASIC Physical Design, ASIC design, engineering or a related field.
Foundational knowledge of ASIC physical design and implementation flows gained through academic projects, internships, or relevant coursework.
Understanding of physical design concepts, including floor planning , clock tree synthesis, power distribution, and I/O planning.
Exposure to the physical design lifecycle, including logic synthesis, placement, routing, and basic timing closure.
Preferred Qualifications
Proficiency in scripting languages such as Python, Tcl , or Perl for task automation and data analysis.
Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus , Synopsys ICC2, or Synopsys Design Compiler) through lab work or internships.
Familiarity with physical verification processes (DRC/LVS) using tools such as Mentor Calibre or Synopsys ICV.
Exposure to static timing analysis concepts and tools, such as PrimeTime .
Pourquoi Cisco?
Chez Cisco, nous révolutionnons la façon dont les données et les infrastructures se connectent et protègent les entreprises à l’ère de l’intelligence artificielle et au-delà. Nous innovons sans crainte de manquer quelque chose depuis 40 ans pour créer des solutions qui optimisent la collaboration entre les humains et la technologie dans les mondes physiques et numériques. Ces solutions offrent aux clients une sécurité, une visibilité et des analyses inégalées sur l’ensemble de l’empreinte numérique.
Alimentés par la profondeur et l’étendue de notre technologie, nous expérimenterons et créons des solutions significatives.…