Job Details:
Job Description:
Job Description:
This position is in the Logic Technology Development (LTD) team, working in one of the most advanced semiconductor development facilities in the world.
The LTD Resolution Enhancement Technology (RET) team is extending the limits of feature sizes that are patternable on Intel's devices, using current and future lithography manufacturing tooling. The team works closely with fab integrated lithography process and mask manufacturing teams using computational lithography tooling to optimize mask patterns and maximize manufacturing process capability. The RET team also works closely with the design rule definition teams, using lithography and patterning simulation capabilities to determine design rules for future Intel process nodes.
What We Offer:
We foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We give you opportunities to transform technology and create a better future, by delivering products that make the world a better place.
Responsibilities include:
Optical Proximity Correction (OPC) algorithms
Development, and implementation of Resolution Enhancement Techniques (RET) for existing and novel process technologies
Define and selects new approaches and implementation of RET
OPC recipe code optimization and validation
Algorithmic design pattern layout manipulation
Use predictive modeling, statistics, machine learning, and other data analysis techniques to collect, explore, visualize fab process data, and develop RET software algorithms and applications to compensate for physical effects in photolithography imaging and the etch pattern transfer process
Support of production mask tapeout and RET validation
Maintain a deep knowledge of state-of-the-art principles and trends in RET and semiconductor technology
Creation of technical documentation and presentations
Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Minimum Qualifications:
Bachelor's degree in a relevant field (e.g., Computer Science, Software Engineering, Electrical Engineering) with 6+ years of professional experience in the semiconductor industry
OR
Master's degree in a relevant field (e.g., Computer Science, Software Engineering, Electrical Engineering) with 4+ years of professional experience in the semiconductor industry
OR
Ph.D. in a relevant field (e.g., Computer Science, Software Engineering, Electrical Engineering) with 2+ years of professional experience in the semiconductor industry
Hands-on professional experience includes one or more of the following:
Pattern synthesis and mask layout manipulation
Knowledge of OPC concepts and capabilities
Preferred Qualifications:
Understanding of the latest techniques for developing and optimizing OPC rule-based synthesis solutions to support both high volume and newly developing technology nodes
For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation…