About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Focus on developing and supporting parasitic extraction flows, with strong hands-on experience in Cadence Quantus and/or Synopsys StarRC, including extraction setup, validation, debugging, post-layout flows. It covers advanced FinFET, BiCMOS, SiGe, and SiPho technologies.
What You Can Expect
Architecting and supporting next-generation automated AMS design flows used across Marvell design teams.
Build and maintain custom tools, PCells, Pycells, GUI utilities, and automation/productivity tools using scripting languages within the Cadence Virtuoso, Synopsys OptoCompiler and Siemens Calibre environments.
Install, validate, and support foundry PDKs.
Set up and maintain physical verification flows and parasitic extraction.
Partner with analog designers and EDA vendors to troubleshoot and resolve complex design flow challenges.
Help shape company-wide CAD infrastructure and best practices for analog, mixed-signal, and silicon photonics development.
What We're Looking For
BSEE with 10–15 years of professional experience, or MS/PhD in Electrical Engineering with 5–10 years of industry experience.
Proven experience building and maintaining analog/mixed-signal design flows for advanced FinFET, BiCMOS, SiGe, and SiPho technologies.
Strong hands-on experience with industry-standard AMS design tools, including Cadence Virtuoso Studio, Synopsys OptoCompiler and Siemens Calibre.
Solid understanding of analog/mixed-signal design flows, including schematic capture, simulation, parasitic extraction, post-layout verification and EMIR.
Programming or scripting experience in Python, TCL, Shell and SKILL.
Experience developing custom CAD automation or verification frameworks.
Familiarity with silicon photonics design flows.
Excellent communication skills and the ability to collaborate effectively with cross-functional teams.
Expected Base Pay Range (USD)
150,680 - 225,700, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR…