About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell’s Optical DSP (ODSP) team within the Connectivity Business Unit develops advanced, industry-leading ASICs for the hyperscale data center, enterprise, and AI infrastructure markets. Our products — including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers — are critical enablers for efficient, high-bandwidth data transmission across fiber optical networks and electrical interconnects at 100G+ per lane.
The ODSP team operates at the leading edge of semiconductor technology, developing chips in TSMC advanced process nodes. We are a global, multi-site engineering organization spanning Santa Clara, Ottawa, Pavia, Irvine, Vietnam, and Argentina — and we are looking for a senior experienced technical leader to serve as a DFT Lead on our next-generation ODSP programs.
What You Can Expect
The position will be responsible for Architecting, Leading and implementing DFT / Test methodology on a complex mixed signal SOC for multiple generations
The execution involves Design-for-Test Architecture definition, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space.
In this position, the responsibility also includes mentoring, guiding and driving a full team of DFT engineers enabling them for scaling across multiple designs.
The position involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test.
What We're Looking For
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience.
Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience.
Hands on working experience in various stages of DFT-Execution - SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bringup/Debug
Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs.
Strong fundamentals in Digital Circuit Design and Logic Design is required
Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)
Prior experience in ASIC design is a plus
Scripting skills using Python, PERL, Tcl and C-Shell is plus
Expected Base Pay Range (USD)
182,360 - 273,200, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support…