Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Micron’s Non-Volatile Engineering Group (NVEG) develops best-in-class NAND memory products in die size, performance, reliability and power! NVEG is embedding AI across the entire design flow, and we are looking for engineers who use AI daily and actively reshape engineering workflows around it.
Position Overview:
As a Principal Design Engineer on the NAND datapath team, you will lead architecture and design of the internal datapath between the page buffer and IO: wave-pipelined buses, flop-to-flop timing, FIFOs, dataline sensing, column repair and clocking. You will use AI daily to accelerate design, timing closure and verification, help bring STA-based semi-custom methodology into a simulation-only flow, and set technical direction as a recognized leader!
What’s Encouraged Daily:
Datapath architecture: Define, design and verify internal datapath blocks (page buffer-to-IO data buses, wave pipelines, FIFOs, SER/DES front ends and datapath clocking) to meet bandwidth, timing and power targets.
Timing closure: Architect and close wave-pipelined and flop-to-flop paths, including setup/hold, skew/jitter budgets, PVT delay tracking, and delay trims across PVT and aging.
Dataline sensing: Design dataline sense amps and precharge/latch sensing, covering offset, Monte Carlo/high-sigma margin, coupling and IR drop.
Array repair & redundancy: Design column repair, fuse/repair storage and redundancy muxing with no bandwidth or timing penalty; verify all repair configurations with test, PE and FW.
Use AI daily for RTL generation, scripting, and timing/waveform analysis. Develop specs and checklists that AI can process. Build agents to automate timing, Monte Carlo, and repair-coverage checks.
Semi-custom methodology: Lead the move from SPICE-only closure to a semi-custom flow with characterized custom cells, SDC/STA sign-off, STA-to-SPICE correlation, and synthesis/APR/ECO flows.
Physical co-design: Drive floorplan, bus routing and RC-aware delay matching with layout, and correlate post-layout timing.
AI & technical leadership: Champion AI adoption and standard processes, define interface specs with multi-functional teams, support silicon debug, and mentor engineers.
Minimum Qualifications:
BS/MS in EE or related field with 8+ years in memory datapath, SRAM or high-speed custom design.
Deep expertise in flop-to-flop and wave-pipelined timing closure (setup/hold, skew, min/max delay, PVT margin).
Experience in sense amp, dataline or SRAM read/write design, including Monte Carlo/high-sigma verification.
Proven collaboration with layout on floorplanning, extraction and post-layout timing correlation.
Daily hands-on AI use, with concrete examples of AI-based workflows (prompts, scripts or agents) that improved productivity or design outcomes.
Preferred Qualifications:
NAND/DRAM/SRAM periphery experience: page buffer, column decoder, global data bus, or array-to-IO pipeline.
Memory repair and redundancy design, and its impact on yield, area, timing and test time.
Timing-adjustment techniques (delay trims, DLL/DCC, training) and aging effects (NBTI/HCI).
Building AI agents, LLM/RAG pipelines or ML models for IC design, verification or debug.
Sophisticated CMOS device physics, mismatch modeling (BSIM), and low-power techniques (clock/power gating, leakage).
Solid understanding of STA and semi-custom flows mixing custom and standard-cell logic.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$181,000.00 - $308,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting…