Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Overview:
Micron is seeking an experienced SRAM Design Engineer to develop high-performance, low-power embedded memory IP and testchip content. This is for advanced semiconductor technologies. The engineer will contribute across the complete memory-development lifecycle, including architecture definition, transistor-level circuit build, composing detailed circuit diagrams, layout interface, SPICE verification, timing and power characterization, compiler enablement, and pre- and post-silicon validation.
The role requires strong hands-on knowledge of SRAM and register-file design, memory arrays and bitcells, read/write datapaths, sense amplifiers, address decoding, control logic, assist techniques, and PPA tradeoffs. The candidate will work closely with teams handling layout development, CAD tools, manufacturing processes, testchip, product, silicon-test, and foundry. They will develop reliable , production-ready memory solutions and correlate models with measured silicon behavior.
Key Responsibilities
• Design and optimize custom SRAM, register-file, and embedded-memory circuits from architecture through schematic, layout support, characterization, and release.
• Develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, clocking, redundancy hooks, and read/write datapaths.
• Evaluate bitcell and peripheral-circuit stability , performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.
• Own transistor-level simulation and signoff using HSPICE, Spectre, FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulatio and waveform/debug reviews.
• Drive SRAM PPA optimization through circuit sizing, architecture selection, banking and muxing decisions, assist techniques, bias strategies, retention modes, and critical-path analysis.
• Define timing, power, noise, and functional characterization methodologies and generate validated data for memory models, compiler views, SoC integration, and product signoff.
• Partner with layout engineers on floorplanning, bitcell-array composition, matching, critical-net routing, clock,also control distribution, parasitic reduction, and layout-dependent effects.
• Support memory-compiler development by defining legal configurations, architecture templates, circuit collateral, generation rules, validation checks, and release-quality views for multiple macro instances.
• Develop or improve automation for macro assembly, simulation setup, corner execution, results extraction, characterization, validation, and regression using Python, Tcl, Perl, SKILL, or similar languages.
• Plan and support SRAM testchips , including memory-instance selection, PPA objectives, test access, measurement structures, characterization plans. Alignment with process-learning goals.
• Lead pre-silicon verification , silicon bring-up, post-silicon characterization, failure debug, and model-to-silicon correlation in partnership with product and silicon-test teams.
• Create clear circuit specifications , design-review material, verification plans, characterization reports, and release documentation with traceable assumptions and decisions.
• Mentor engineers on memory-circuit fundamentals, simulation field, PPA analysis, debug methods, and reusable build practices.
• Explore AI-assisted engineering workflows for specification extraction, circuit and block partitioning, test-mode enrichment, design-flow automation, regression analysis and documentation while maintaining human technical review.
Technical…