About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
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To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
About the Role
SiFive is looking for a Senior Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs.
This is a T3 / Senior Engineer individual-contributor role within the Interconnect horizontal area, focused on coherent interconnect and related subsystem behavior.
In this role, you will work across architecture, RTL, formal, and design verification teams to verify coherent data movement, protocol correctness, ordering, flow control, quality-of-service behavior, and subsystem integration across multiple interface types and bridge paths.
We are looking for someone who can independently execute high-quality verification work, build robust environments, debug complex issues efficiently, and contribute to stronger verification methodology across the broader interconnect verification effort.
Responsibilities
Understand the coherent interconnect architecture and create effective verification strategies and test plans for the assigned area.
Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, and error handling.
Verify subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, including conversion, buffering, deinterleaving, and related data-movement behavior.
Define and execute directed and constrained-random tests that expose corner cases in coherency, concurrency, ordering, credits, arbitration, QoS behavior, and integration scenarios.
Analyze failures, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
Collaborate closely with architecture, design, formal, and software teams to clarify requirements, review specifications, and improve verification quality early in the development cycle.
Write functional coverage, analyze coverage results, and close coverage holes to ensure verification completeness and signoff quality.
Contribute reusable methodology, automation, and debug improvements that raise team-wide productivity and verification quality.
Minimum Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
5+ years of relevant experience in IP, subsystem, or SoC functional verification, preferably in coherent interconnect, cache, memory-system, or CPU-subsystem verification.
Strong hands-on experience with SystemVerilog and UVM-based verification.
Solid understanding of cache-coherent systems, on-chip interconnects, memory-subsystem…