About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
About the Role
SiFive is looking for a Staff Design Verification Engineer to drive verification of high-performance CPU core functionality, with meaningful scope in RISC-V Vector Extension (RVV) and vector microarchitecture verification.
This is a Staff individual-contributor role within the CPU Design Verification organization, focused on high-performance out-of-order CPU core development.
The role spans key core areas such as Frontend, Midcore, Load-Store Unit, Hardware Prefetch, and Vector Unit / vector microarchitectural interactions, and is aimed at an engineer who can independently own complex verification problems, define verification strategy early, identify microarchitectural risk, and raise verification quality across the broader CPU DV effort.
You will work closely with architecture, RTL, performance, and verification teams to ensure design intent is captured correctly, difficult corner cases are verified thoroughly, and signoff quality is achieved with strong technical judgment and scalable methodology.
Responsibilities
Own verification planning and execution for one or more high-performance out-of-order CPU core areas, from block-level verification through core-level integration and signoff.
Drive verification strategy, test planning, debug, coverage analysis, and closure for complex CPU features and microarchitectural interactions.
Define effective verification approaches for challenging behaviors such as branch prediction, instruction fetch, issue and dispatch behavior, pipeline interactions, hazard handling, load/store ordering, memory consistency, exception and recovery behavior, hardware prefetch correctness, and vector execution correctness.
Drive verification of RVV and vector-unit functionality, including vector arithmetic, vector memory operations, masking behavior, configuration-dependent execution, hazard handling, exception behavior, and scalar-vector interactions.
Verify vector microarchitectural behaviors involving SEW, LMUL, VL, VSTART, masking, vector register-file behavior, vector memory sequencing, and interaction with scalar pipeline and cache / memory hierarchy behavior.
Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.
Partner closely with architecture and design teams from early feature-definition stages to review specifications, identify ambiguity, and improve design debugability and verification completeness.
Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
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