- Where
- Sunnyvale, California, United States
- Level
- Senior
We Are At Synopsys, we drive the innovations shaping the Era of Pervasive Intelligence, enabling everything from autonomous systems to advanced AI compute. Our leadership in chip design, verification, and IP integration powers the world’s most demanding silicon. Join us to build industry-leading SerDes IP that defines next-generation connectivity.
You Are You are a Principal-level analog design leader with deep expertise in high-speed SerDes and silicon-proven analog macros. You operate at the architecture and system boundary, translating standards and product requirements into robust, scalable circuit and layout implementations. You lead through technical influence by setting direction, driving alignment across teams, and mentoring engineers to deliver high-quality outcomes. You are recognized for sound judgment in power, area, and performance trade-offs, disciplined verification methodology, and the ability to resolve complex cross-domain issues spanning analog, digital calibration and control, and physical design. You communicate clearly with internal stakeholders and customers, presenting data-driven decisions and guiding technical reviews with authority and clarity.
What You’ll Be Doing • Own macro-level architecture, design, and implementation of critical analog circuits for SerDes IP across TX, RX, and clock paths. • Interpret SerDes standards and system architecture to define detailed analog specifications, budgets, and design targets including jitter, noise, linearity, settling, latency, power, and area. • Drive top-level architecture trade-offs and define scalable circuit platforms reusable across product variants and process nodes. • Lead and track technical execution across multiple sub-block owners, identify risk early, remove blockers, and ensure alignment to schedule and product goals. • Define clear interfaces between analog macros and digital calibration, adaptation, and control, partnering with RTL and firmware teams to co-define algorithms and observability hooks. • Define and enforce robust verification strategies using advanced SPICE and simulator capabilities including corner and Monte Carlo analysis, aging, mismatch, noise, transient jitter, PVT sweeps, and reliability checks. • Champion best practices in modeling including Verilog-A behavioral models to accelerate system validation and improve correlation between block and top-level results. • Drive silicon correlation plans by defining key measurements, mapping results to simulations, and feeding learnings back into design improvements. • Provide technical oversight to physical layout to minimize parasitics, coupling, device stress, and process variation sensitivity, ensuring reliability and ESD are addressed from the start. • Guide FinFET layout strategies for mismatch, symmetry, routing, shielding, EM and IR, and high-speed interconnect integrity. • Present architecture rationale, simulation results, and risk assessments in peer and customer reviews, responding to technical questions with data-backed clarity. • Consult on electrical characterization and test strategy for SerDes IP macros, influencing DFT and bring-up hooks and lab debug workflows. • Mentor junior and mid-level engineers, setting a high technical bar for design quality, documentation, and review rigor. • Contribute to team capability through reusable collateral, methodology improvements, and onboarding practices as the organization scales.
The Impact You Will Have • Set technical direction for key SerDes analog macros, enabling best-in-class performance and reliability for next-generation standards. • Improve predictability and quality through stronger verification methodology, correlation strategy, and design reuse. • Elevate cross-functional execution across analog, layout, and digital teams, reducing integration risk and accelerating tapeout readiness. • Provide technical leadership in customer engagements, strengthening Synopsys’ reputation for silicon-proven IP. • Develop…