We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent 15+ years in the trenches of physical design, and you know that the difference between a chip that tapes out and one that stalls in timing closure is usually a methodology decision made six months earlier. You are the engineer who catches that decision before it becomes a crisis. You have worked directly with customers enough to know that the best solution is not always the most elegant one, it is the one that actually works in their flow, with their constraints, on their timeline.
You think in terms of PPA, runtime, and design closure, but you also think about the engineer who will inherit this methodology next quarter. Automation is not a buzzword for you, it is how you multiply impact. You write Python and Tcl not because it is in the job description, but because waiting for someone else to build the tool you need is not an option.
You do not just solve problems, you translate customer pain into product requirements that R&D can act on. You have sat in rooms with foundry partners, product teams, and customer architects, and walked out with a plan that everyone believes in. At Synopsys, you will work on implementation challenges that define what is possible at 5nm and below, with a team that takes this work as seriously as you do.
What You'll Be Doing
Lead physical design engagements for strategic semiconductor customers working on advanced-node designs, from floorplanning through signoff
Develop and optimize RTL-to-GDSII methodologies that improve PPA, reduce runtime, and accelerate design closure for production tapeouts
Build automation frameworks using Python and Tcl that solve real productivity bottlenecks in placement, CTS, routing, and timing closure workflows
Collaborate with Product Engineering and global R&D teams to validate new Synopsys implementation technologies and translate customer feedback into product requirements
Drive technical evaluations and benchmarking programs that demonstrate measurable improvements in customer design metrics
Support advanced-node enablement and DTCO initiatives in partnership with foundries and customer design teams
Mentor engineers across the Korea team and contribute to technical leadership on methodology development and customer engagement strategy
The Impact You Will Have
Enable successful tapeouts for leading semiconductor companies working on AI accelerators, mobile SoCs, HPC, and memory designs at 5nm and below
Deliver methodology improvements that directly reduce customer design cycle time and improve power, performance, and area outcomes
Influence the product roadmap for Synopsys implementation tools based on real customer needs and advanced-node challenges you identify
Accelerate engineering productivity across customer teams through automation solutions that eliminate manual bottlenecks in physical design flows
Build long-term technical partnerships with strategic customers that drive adoption of Synopsys technologies and expand deployment across their design organizations
Shape the future of physical design methodologies by integrating emerging technologies like AI-assisted workflows into production-ready solutions
Grow technical capability within the Korea team through mentorship and knowledge sharing that elevates the entire organization
What You'll Need
BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field
15+ years of hands-on experience in semiconductor physical design, implementation methodologies, or EDA development
Deep expertise across the RTL-to-GDSII flow including…