- Pay
- $3,000/mo
- Where
- Europe · Remote · Remote
- Level
- Senior
Solid commercial experience in FPGA and/or ASIC digital design using SystemVerilog Strong hands-on skills in RTL design, timing analysis/closure, and low-latency architectures
Experience with high-speed interfaces (AXI, PCIe, DDR or similar) is a big plus
4 months+, Direct Hire