About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell’s Optical DSP (ODSP) team within the Connectivity Business Unit develops advanced, industry-leading ASICs for the hyperscale data center, enterprise, and AI infrastructure markets. Our products — including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers — are critical enablers for efficient, high-bandwidth data transmission across fiber optical networks and electrical interconnects at 100G+ per lane.
The ODSP team operates at the leading edge of semiconductor technology, developing chips in TSMC advanced process nodes. We are a global, multi-site engineering organization spanning Santa Clara, Ottawa, Pavia, Irvine, Vietnam, and Argentina — and we are looking for a senior staff DFT engineer in Santa Clara on our next-generation ODSP program, to help set up the methodology and flow on our flagship products.
What You Can Expect
Define DFT architecture and implementation for a block within the chip, including hierarchical DFT, test modes and clocking.
Plan, partition and integrate IP-level DFT (SerDes, PLL, memories, third-party IP).
Drive ATPG coverage, test-time and pattern-count targets; optimize compression and power during test.
Lead DFT sign-off: DRC, simulation, timing, equivalence, and handoff to PD/ATE.
Debug silicon: failure isolation, diagnosis, yield learning with Product/Test engineering.
Mentor junior engineers; review their work; coordinate with design, verification, PD, and test.
Improve methodology and automation.
What We're Looking For
BS in EE/CE with 8+ years or MS in EE/CE with 5+ years of DFT experience on complex SoCs, with multiple tape-outs and silicon bring-ups
Deep expertise in scan, compression, ATPG fault models, MBIST/repair, JTAG, and at-speed test.
Strong DFT timing/STA knowledge; experience with advanced nodes (7nm and below preferred).
Proven independent problem solving and mentoring.
Experience with high-speed SerDes/DSP products is a plus.
Expected Base Pay Range (USD)
134,390 - 201,300, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran…